1. Field of the Invention
The invention pertains to the field of heat treating materials using microwave energy. More particularly the invention pertains to apparatus and methods for heating silicon wafers while monitoring the wafer temperature.
2. Description of Related Art
Furnace annealing is a process used in semiconductor device fabrication wherein a batch of semiconductor wafers is heated in order to affect their electrical properties. Wafers can be heated in order to activate dopants, change film-to-film or film-to-wafer substrate interfaces, change states of grown films, densify deposited films, repair damage from implantation, diffuse dopants or drive dopants from one film into another or from a film into the wafer substrate. Because these furnaces are capable of processing large batches of wafers at a time each process may last from several hours up to a day.
It was predicted that 300-mm wafers marked the end of furnace era. Although there has been a move toward single-wafer systems for Rapid Thermal Process (RTP) or Anneal (RTA), the furnace based anneals haven't disappeared and there has been a strong base of furnace processes required for 300-mm wafers. The RTP or RTA processes have thermal cycles for each wafer that is of the order of minutes rather than hours for furnace anneal. Rapid thermal annealing is applied to UltraShallow Junctions (USJ), silicide formation and oxidation.
UltraShallow Junctions
Semiconductor fabrication processes use many steps of ion implantation to create a completed semiconductor device. The primary parameters of ion implantation are species (N-type and P-type), energy and dose. N-type dopants are usually arsenic or phosphorus and P-type doping is usually boron. The energy determines how deep the ions go into the silicon. Higher energy implants go deep while low energy implants are shallow. The dose determines how conductive the layer will be when complete. All of these parameters are chosen by the transistor designer for each implant step to optimize the device characteristics.
During the ion implantation process the heavy ions easily knock out silicon atoms and silicon crystal structure is damaged. The wafer and fabricated devices need to be annealed to activate the dopant and provide conductivity. Key elements in forming USJ are junction depth and sheet resistance, and process manufacturability and repeatability. These shallow junctions demand low thermal budgets, requiring processing at a high ramp rate with minimal peak temperature overshoot. The steep thermal profiles give the best junction characteristics by limiting dopant diffusion but challenges the ability to deliver consistent process uniformity and repeatability. The primary challenge is production worthiness, measured by within-wafer uniformity and wafer-to-wafer repeatability, to get product yield from the wafer edge especially as device geometries shrink, where an even shallower junction must be ensured.
Nickel Silicide
Metal silicides have been widely applied to IC fabrication because of their high melting points and low resistance. As the critical dimensions for contact area and source/drain regions are getting smaller and smaller nickel silicide is emerging to be the choice of material over cobalt and titanium silicide. Nickel silicide is fabricated by first forming a thin film of nickel, for instance by evaporating or sputtering, on the selected area of the semiconductor substrate. The semiconductor substrate is then heated so that the thin nickel film reacts with silicon to form the silicide layer. Another advantage in the formation of NiSi is that it consumes considerably less Si from the substrate as compared to cobalt silicide.
However, the nickel-silicon system has various phases (i.e., the phase diagram is more complex than the Co—Si system) and typically undergoes phase transformation during the heating cycle. Table I below shows these phases and some of the physical properties such as the resistivity and their melting temperatures, average Young's modulus and average coefficient of thermal expansion (CTE).
TABLE 1Comparison of some physical properties of Ni, silicide phases, and Si.The average CTE and Young's Modulus represent values for polycrystallinethin films and can vary significantly in the crystalline direction.PhaseNiNi3SiNi31Si12Ni2SiNi3Si2NiSiNiSi2SiCrystalCubicCubicHex.Orth.Orth.Orth.CubicCubicStructureResistivity7-1080-9090-15024-3060-7010-1834-50Dopant(μΩcm)dependentTransformation/14551035/117012421255/1306830/845992981/9931414Melting (° C.)Avg. Young's200139177161167132130-187Modulus (GPa)Avg. CTE thin13.49.016.5~122.6films (×10−6/K)(Adapted from Silicide Technology for Integrated Circuits, By L. J. Chen, Institute of Electrical Engineers)
Among all the phases listed above the lowest resistivity NiSi is the desired silicide phase for contacts to a semiconductor device. Because there is phase transformation occurring during the heating or annealing cycle, there is a need to monitor the temperature of the substrate as well as the formation of the desired phase.
The crystallographic orientation changes during the thermal exposure, thus techniques such as X-ray reflectance (XRR) and X-ray diffraction (XRD) are used to record the crystalline structure of the phases. During the phase transformation from Ni to silicides, Ni3Si is generally the first silicide to form, but it may not be easily detected using XRD since both Ni and Ni3Si have a cubic lattice structure. The first silicide phase that can be distinctly identified with XRD is Ni31Si12, which has a hexagonal structure. Similarly, the identification of NiSi will not be easy since the Ni2Si and Ni3Si2 phases are also orthogonal. However, the resistivity of each phase varies significantly, therefore the X-ray data and resistivity measurements together help in identification of the desired phase.
Oxidation
Insulating dielectric layers are a key element in semiconductor device fabrication, which provide isolation between conductive layers on the surface of the wafer. In fact, one of the most important reasons silicon has become such a successful medium for integrated microelectronics is that silicon oxidizes and forms a good native oxide, SiO2. At elevated temperatures (800-1200° C.) the oxide grows quickly and the advantage of native thermal oxides is that they have similar material properties (e.g. thermal expansion coefficient, lattice size, etc.) of the native material. The oxide growth does not create significant stresses in the material that can lead to serious problems including circuit failure. Oxidation can be carried out in a dry or wet environment. Wet oxidation is preferred over dry oxidation for growing thick oxides, because of the higher growth rate. However, fast oxidation leaves more dangling bonds at the silicon interface, which allows current to leak along the interface. Wet oxidation also yields a lower density oxide with lower dielectric strength. Since a long time is required to grow a thick oxide in dry oxidation, thicker oxides are usually grown with a short dry cycle followed by long wet oxidation and then another short dry oxidation (a dry-wet-dry cycle). The beginning and ending dry oxidations produce films of high-quality oxide at the outer and inner surfaces of the oxide layer, respectively.
Rapid thermal processing has been applied to all the processes described above. Lamp-based RTP spike-anneal has enabled recent production while laser spike-anneal (LSA) is emerging and even being claimed as the process of record for current high performance semiconductor device manufacturing.
In a production environment, flexibility to handle wafer variations with different emissivities and product types is essential. The high temperature spikes may also lead to warping of the wafer and uncontrollable strain in the device structure. Thus the successful integration of any type of anneal requires controlled, low thermal budget history to ensure minimal deformation and process-induced stresses.
In view of some of the above concerns, there is a clear need for improved annealing processes and reliable in-situ monitoring of the progress of the process.
Objects and Advantages
Objects of the invention include: providing a rapid processing method for annealing semiconductor devices; providing a method for monitoring a rapid thermal annealing process; providing a method for monitoring a microwave heating process; providing a method for in situ process control based on real-time measurement of emissivity; providing a method for lower temperature anneal rather than a temperature spike anneal; providing a method for thermal treatment that reduces stress and warpage of the workpiece; providing a method for thermal treatment having in-situ feedback and lower process temperatures, providing a method for thermal treatment that reduces temperature excursions; and, providing a method for thermal treatment that is suitable for automated control based on the feedback of process status.